Few days back, I was in search of a free tool which could run my Verilog-A models. I was looking for different options and QUCS, ngspice were some of them. However, none of them were straight forward for compiling and simulating the Verilog-A models. Later, while visiting SemiWiki.com, I found this article, which lead me to an awesome toolkit which has a free version too.
The tool name is Symica IC design toolkit, available here. A free version of toolkit can be found here. As the table shows in the page, the free version allows user to perform a SPICE simulation of a circuit with up to 300 nodes. In addition, the free version supports Verilog-A simulations. The tool was very easy to use and is similar to Cadence Virtuoso product. The tools is available for download for Windows and Linux platforms.
As my major reason for my search was a free tool for simulating Verilog-A, so I went straight to my objective. Creating a new library and adding different Cell views was very simple and straight forward.
I created a voltage amplifier for my test case, saved it and created a symbol view for my Verilog-A model. Then I moved to create my testbench schematic. All this is a very smooth experience if you are familiar with the Cadence Virtuoso environment.
Next task was to setup the simulation and run it. Selecting the waveforms to plot was similar as found in ADE tool from Cadence. The tool compiles the Verilog-A model using the ADMS, which is a FOSS project. ADMS converts the Verilog-A model into simulator dependent C code which can be compiled as a model for the simulator. Although, ngspice and QUCH also use the same interface, they do not allow the model compilation in run time. This tool was very smooth in its job and successfully compiled the model and presented the simulation results.
The result window appears as soon as the simulation is completed. It has markers which works in a similar was as PSpice markers. It has plenty of measurement functions, support for eye diagrams and histograms etc.
Overall, in my view, it was an easy to use tool, which I can continue to use for simulating my Verilog-A models. If you have used this tool, let me know your experience here in comments.