Verilog Simulation using Icarus Verilog

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits.

This article will take you through simulation of a basic module using Icasrus Verilog. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the vvp command. For synthesis, the compiler generates netlists in the desired format.

Installing Icarus Verilog

For installing Icarus Verilog the procedures vary with platforms.To find a proper installation method for you plate for you may visit here. Icarus Verilog builds for Windows can be downloaded from here. In Ubuntu Linux you can download it using sudo apt-get install iverilog. Remember this command might not install the latest release of Icarus Verilog. You can use a method at above mentioned link to install Icarus Verilog simulator in your system.

Running Icarus Verilog

First we will write a traditional small Hello World program. Enter following lines of code in a plain text editor and save it as hello.v .

//A traditional starter
module main;
  initial
    begin
      $display("Hello, World");
      $finish ;
    end
endmodule

Open a command window and type

iverilog -o hello hello.v

vvp hello

This should generate following output:

Hello, World

This completes the simulation of our first basic program in Verilog using Icarus Verilog. In next article we will simulate a basic circuit using Icarus Verilog and use GTKWave to view our outputs.

Reference:

Verilog

Icarus Verilog: Wikia